This application claims the priority benefit of Taiwan application serial no. 89119205, filed Sep. 19, 2000.
1. Field of Invention
The present invention relates to a ball grid array package. More particularly, the present invention relates to a ball grid array package having a heat dissipation structure therein.
2. Description of Related Art
The development of semiconductor devices is always aiming towards a higher level of integration and a higher density package so that more functions can be packed inside each electronic product. Due to a rapid increase in the data processing speed, the signal frequency of each semiconductor device is higher. Together with a high level of packing density within a semiconductor package, the amount of heat generated per unit time per unit volume is increased considerably. Consequently, how to increase the heat dissipation rate of a package has become an important topic in the semiconductor production circle.
Ball grid array (BGA) is a type of package capable of providing a high pin count connection with external devices. Since solder balls are used in a BGA package, the signal path is greatly reduced and hence widely adopted by the integrated circuit package industry. However, most BGA package has a high pin count and has a high heat output. Hence, increasing the heat dissipation rate of a BGA package has been a major topic of research for some time. In addition, most BGA packages use laminated boards as carriers. Since the coefficient of thermal expansion (CTE) between the silicon chip and the laminated board is rather different, package deformation can be frequent. This will not only lead to a large thermal stress on the solder balls, but will also lead tosolder ball joint failure after a few thermal cycles.
As disclosed in U.S. Pat. No. 5,216,278, the heat generated from the chip is dissipated from the die pad, vias and thermal balls to the printed circuit board. However, the number and the arrangement of these thermal balls are limited. As disclosed in U.S. Pat. No. 5,894,410, the thermal balls are arranged within the area covered by the chip except the edge region of the chip in order to reduce the influence of the stress on the thermal balls.
FIG. 1 is a schematic cross-sectional diagram of a conventional ball grid array. As disclosed in U.S. Pat. Nos. 5,216,278 and 5,894,410, a conventional ball grid array package 100 is build upon a laminated board 102. The laminated board 102 is constructed out of a multiple of patterned trace layers 104 and 106 and an insulation layer 108 stacking over each other. The patterned trace layer 104 includes a die pad 110 and other trace lines. The backside 124 of a silicon chip 120 is attached by an adhesive material 112 to the die pad 110. The bonding pads 126 on the active surface 122 of the chip 120 are electrically connected to the patterned trace layer 104 by gold wires 114. Molding compound 134 encapsulates the chip 120 and the junction between the chip 120 and the patterned trace layer 104. The patterned trace layer 106 has a plurality of ball pads 116 and 118 for attaching solder balls 130 and 132. The solder balls 130 are used for transmitting electrical signals and are attached to the contacts 142 of a printed circuit board (PCB) 140. The ball pads 116 are electrically connected to other lines in the patterned trace layer 104 by vias 146. A plurality of vias 148 each passing through the laminated board 102 and in connection with the ball pads 118 is generally formed under the die pad 110. The main purpose of the solder balls 132 is to dissipate heat away by transferring the heat to the heat dissipation points 144 on the printed circuit board 140. The solder balls 132 mainly serve as ground or power source contacts. Thus in a conventional BGA package, the number and the arrangement of the thermal balls are limited. Hence, the quantity of heat capable of being dissipated is quite limited and may not be large enough to carry away all the heat generated in a high heat generation package. Furthermore, these thermal balls are normally placed within the area covered by the chip and set a distance away from the edge region of the chip. Hence, the solder balls in the package are not arranged in a full area array.
Accordingly, one object of the present invention is to provide a ball grid array (BGA) package with improved heat dissipation.
Another object of the present invention is to provide a ball grid array (BGA) package having solder balls arranged in a full area array, which results in improved heat dissipation.
Still another object of the present invention is to provide a ball grid array (BGA) package in which the thermal balls can be arranged on the whole lower surface of the package, including the edge region of the chip so that solder ball joint failure will not occur.
Still another object of the present invention is to provide a heat dissipation type of ball grid array (BGA) package. The package has solder balls inserted into the space between the underside of a silicon chip and the signal balls of the package. In addition, through conductive trace lines to thermal balls connection, another heat dissipation path is provided so that the heat dissipation rate is increased.
Still another object of the invention is to provide a heat dissipation ball grid array package by having a dissipation ring around the periphery on the underside of a silicon chip. Moreover, solder balls are attached to the dissipation ring as another heat dissipation path, and thereby increasing the heat dissipation capacity of the package.
To achieve these and other advantages in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a heat dissipation ball grid array (BGA) package. The BGA package includes a substrate having a plurality of patterned trace layers and an insulation layer between neighboring patterned trace layers. The first patterned trace layer on the upper surface of the substrate has a die pad. The second patterned trace layer on the lower surface of the substrate has signal ball pads, first thermal ball pads, second thermal ball pads and conductive trace lines. The first thermal ball pads and the second thermal ball pads are connected by conductive trace lines. The insulation layer has signal vias and thermal conductive vias. The patterned trace layers are electrically connected by the signal vias. The thermal conductive vias link up the die pad and the first thermal ball pads thermally. The backside of the chip is attached to the die pad and the chip is electrically connected to the first patterned trace line. The first thermal ball pads are positioned inside the area covered by the chip. The second thermal ball pads and the signal ball pads are positioned outside the area covered by the chip. Molding compound encapsulates the chip and the junction between the chip and the first patterned trace layer. The signal balls are attached to the signal ball pads. The signal balls are also in contact with some of the contact points on a printed circuit board. First thermal balls are attached to the first thermal ball pads. The first thermal balls are in thermal contact with contact points on the printed circuit board. Second thermal balls are attached to the second thermal ball pads.
According to one preferred embodiment of this invention, the second thermal ball pads can connect with the die pad by a thermal via. The second thermal ball pad can be extended and combined to form a heat dissipation ring located just outside the area covered by the chip. The second thermal balls is further capable of connecting with the contact point on the printed circuit board so that more heat can be conducted away through the printed circuit board. Alternatively, the second thermal balls and the printed circuit board has no direct thermal connection so that heat may be dissipated by thermal convection. Because the second thermal balls and the thermal ring are located outside the area covered by the chip, another path for heat dissipation is created. Since area for heat dissipation is increased, overall heat dissipation rate of a package of standard volume is also increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.